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Espressif Systems /ESP32-S3 /RMT /INT_RAW

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Interpret as INT_RAW

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH0_TX_END)CH0_TX_END 0 (CH2_TX_ERR)CH2_TX_ERR 0 (CH1_TX_THR_EVENT)CH1_TX_THR_EVENT 0 (CH1_TX_LOOP)CH1_TX_LOOP 0 (CH7_RX_END)CH7_RX_END 0 (CH5_RX_ERR)CH5_RX_ERR 0 (CH6_RX_THR_EVENT)CH6_RX_THR_EVENT 0 (TX_CH3_DMA_ACCESS_FAIL)TX_CH3_DMA_ACCESS_FAIL 0 (RX_CH7_DMA_ACCESS_FAIL)RX_CH7_DMA_ACCESS_FAIL

Description

Raw interrupt status

Fields

CH2_TX_END

The interrupt raw bit for CHANNEL2. Triggered when transmission done.
CH3_TX_END

The interrupt raw bit for CHANNEL3. Triggered when transmission done.
CH1_TX_END

The interrupt raw bit for CHANNEL1. Triggered when transmission done.
CH0_TX_END

The interrupt raw bit for CHANNEL0. Triggered when transmission done.
CH3_TX_ERR

The interrupt raw bit for CHANNEL3. Triggered when error occurs.
CH0_TX_ERR

The interrupt raw bit for CHANNEL0. Triggered when error occurs.
CH1_TX_ERR

The interrupt raw bit for CHANNEL1. Triggered when error occurs.
CH2_TX_ERR

The interrupt raw bit for CHANNEL2. Triggered when error occurs.
CH0_TX_THR_EVENT

The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than configured value.
CH3_TX_THR_EVENT

The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than configured value.
CH2_TX_THR_EVENT

The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than configured value.
CH1_TX_THR_EVENT

The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than configured value.
CH2_TX_LOOP

The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the configured threshold value.
CH3_TX_LOOP

The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the configured threshold value.
CH0_TX_LOOP

The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the configured threshold value.
CH1_TX_LOOP

The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the configured threshold value.
CH4_RX_END

The interrupt raw bit for CHANNEL4. Triggered when reception done.
CH6_RX_END

The interrupt raw bit for CHANNEL4. Triggered when reception done.
CH5_RX_END

The interrupt raw bit for CHANNEL4. Triggered when reception done.
CH7_RX_END

The interrupt raw bit for CHANNEL4. Triggered when reception done.
CH7_RX_ERR

The interrupt raw bit for CHANNEL4. Triggered when error occurs.
CH4_RX_ERR

The interrupt raw bit for CHANNEL4. Triggered when error occurs.
CH6_RX_ERR

The interrupt raw bit for CHANNEL4. Triggered when error occurs.
CH5_RX_ERR

The interrupt raw bit for CHANNEL4. Triggered when error occurs.
CH5_RX_THR_EVENT

The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value.
CH7_RX_THR_EVENT

The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value.
CH4_RX_THR_EVENT

The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value.
CH6_RX_THR_EVENT

The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value.
TX_CH3_DMA_ACCESS_FAIL

The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails.
RX_CH7_DMA_ACCESS_FAIL

The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data